The present invention relates to a semiconductor design technology, and more particularly, to a ring oscillator for generating an oscillating clock signal and a multi-phase clock correction circuit for correcting the phase of a multi-phase clock signal using the same.
In general, a semiconductor device, such as Double Data Rate Synchronous DRAM (DDR SDRAM), includes diverse circuits for performing a variety of circuit operations. As one of these diverse circuits, there is a ring oscillator. Typically, the ring oscillator is provided with an odd number of inverters to generate an oscillating clock signal. Recently, however, a ring oscillator with an even number of inverters as shown in FIG. 1 has been mainly employed.
Referring to the circuit diagram of FIG. 1, the existing ring oscillator 110 is provided with multiple inverters to produce first to fourth oscillating clock signals CLK0, CLK90, CLK180, and CLK270, respectively. Since the circuit configuration and operation of the ring oscillator 110 is well-known to those skilled in the art, details thereof will be omitted here for the sake of brevity. Here, the first clock signal CLK0 has a phase opposite to that of the third clock signal CLK180 and the second clock signal CLK90 has a phase opposite to that of the fourth clock signal CLK270. Thus, the second clock signal CLK90 is 90° out of phase with the first clock signal CLK0, the third clock signal CLK270 is 180° out of phase with the first clock signal CLK0, and the fourth clock signal CLK270 is 270° out of phase with the first clock signal CLK0. For reference, each of the first to fourth clock signals CLK0, CLK90, CLK180, and CLK270 oscillates because each inverter has a nonlinear property in operation.
Each of the inverters executes an inversion operation in response to an external power supply voltage applied thereto, to generate first to fourth oscillating clock signals CLK0, CLK90, CLK180, and CLK270. Thus, the first to fourth clock signals CLK0, CLK90, CLK180, and CLK270 oscillate by full swing at a voltage level between the external power supply voltage and ground voltage. That is, these clock signals oscillate at a CMOS level.
Meanwhile, semiconductor devices are designed to operate at high speed and to have low jitter characteristics. Thus, in recent years persons skilled in the art have preferred a clock signal of a Current Mode Logic (CML) level whose swing width is small over a clock signal of a CMOS level. Typically, a CML level clock signal consumes less power in high speed operation and has lower jitter characteristics than a CMOS level clock signal.
However, the existing ring oscillator by its configuration has to generate a CMOS level clock signal rather than a CML level clock signal, and thus, it is not suitable for semiconductor devices of current design.